2015
04.23

Picking up from where I left off last time, that next concern is that we would be increasing the number of adders in an effort to improve the multiplication instruction. Given the “serialized” adder described in the last log, this is not really a problem from a transistor count standpoint.

At this point, it is time to ask a new question: What do those adders do when not doing multiplication?

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2015
04.23

Sarah Wittman describes “simultaneously designing top-down and bottom-up until your designs meet in the middle”. She goes into a little detail on the subject, and I recommend reading what she has to say. Like Sarah’s, my project (as it currently exists) has come together in the middle.

When I first started this effort I had an idea to make what I call a “serialized” processor. The idea was to be able to operate on a stream of bits rather than on a collection of bits. The theoretical advantages of this idea were as follows:

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2015
04.23

Having been introduced to this project, you may have some desire to follow along. I am thrilled at the prospect of having others follow along on this adventure. The possibility that others might find this project helpful or learn from it in some way is an equally thrilling prospect. However, this is an adventure, and as such, there are risks. This post is to serve as fair warning for those that would follow.

As stated in the introduction, this project began in 2009, and has largely taken place in my mind. Up to this point I have written far too little down, which means most of the project details are still in my head. Part of the reason for these project logs is to get these details into a less volatile form of storage, and after six years, there are many details.

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